The present invention relates to a cache memory control system suitable for a data processing device which adopts a segmentation system.
In a data processing device, the operation speed of a main memory unit is slower than the command processing speed of a central processing unit (CPU). In order to prevent a decrease in the processing speed due to the data access of the main memory unit, a high-speed memory called a cache memory is generally arranged to store a copy of part of the data stored in the main memory unit.
In the data processing device of the above architecture, various procedures are proposed to increase a hit ratio of data in the cache memory to the master data in the main memory unit when the CPU accesses data from the cache memory, so as to improve the processing efficiency in cooperation with the cache memory.
For example, the capacity of the cache memory is increased so as not to frequently require substitution. Invalid data in the cache memory is decreased.
Furthermore, in order to decrease parallel access of the processing units (the instruction decoder and the arithmetic and logic unit) in the CPU, a data processing device is proposed wherein an instruction cache memory and data cache memory are separately utilized.
FIG. 1 is a block diagram of a conventional data processing device which has separate instruction and data cache memories. A central processing unit (CPU) 11 and a main memory unit 12 are connected through a memory bus 13. The CPU 11 is functionally subdivided into an instruction decoder 104 and an arithmetic and logic unit 102 which are respectively connected to the memory bus 13 through an instruction cache memory 14 and a data cache memory 15. In this case, the hardware logic determines the use of one of the cache memories according to the status of whether or not the memory access is initiated in the instruction read. The above operation is generally performed independently of the software.
In such a data processing device, however, after an operating system (to be referred to as an OS program hereinafter) runs and the user program is initiated, the OS is removed from the cache memories 14 and 15. When the user program is finished and the user wishes to return to the OS again, the OS is no longer loaded in the cache memories 14 and 15.
FIG. 2 is a block diagram of another example of a conventional data processing device. In this data processing device, the OS may not be removed from the cache memories even if the user program is initiated since an OS cache memory 24 and a user program cache memory 25 are arranged.
However, even in this second example of the conventional data processing device, the OS is too long to be stored in the OS cache memory 24 all at once. Therefore, when the OS is loaded and then the user program is initiated, only the final block of the OS is left in the OS cache memory 24. When the user program is finished and the user wishes to reload the OS, the first block of the program is not present in the OS cache memory 24.
In another example utilized for cache memory selection, since data of the OS is often fixed in a memory location (or in a virtual storage space when the virtual storage system is adopted), it is checked whether the memory addresses generated for the memory access are located in a predetermined range so as to select the desired cache memory.
The desired cache memories are assigned in a predetermined storage area of the memory when the OS is created. However, it is inconvenient to modify the OS.